EN0-001 Online Practice Questions and Answers

A program running on a development board that is connected to a host using a debugger can access a file on the host by using:

A. Memory mapping

B. Semihosting

C. Polling

D. Virtual I/O

When the processor is executing in Thumb state, which of the following statements is correct about the values stored in R15?

A. Bits[31:16] are duplicated with bits[15:0]

B. The PC value is stored in bits[31:1] and bit[0] is treated as zero

C. The PC value is stored in bits[31:16] and bits[15:0] are undefined

D. The PC value is stored in bits[15:0] and bits[31:16] are undefined

Under which of the following data-sharing scenarios would cache maintenance operations be necessary?

A. Sharing data with another thread running on the same core

B. Sharing data with another process running on the same core

C. Sharing data with an external device

D. Sharing data with another CPU in an SMP system

An application contains three calls to an external function, foobar(), which is defined in a shared (or dynamic) library. How many copies of foobar() will the linker place in the application image?

(Ignore linker inlining)

A. None

B. Always one

C. Always three

D. One or more depending on optimization level

Which of the following register values would cause an unaligned access when the instruction LDRH r0, [r1] is executed?

A. R0=0x100, R1 =0x1000

B. R0=0x100, R1=0x1002

C. R0=0x101, R1=0x1002

D. R0=0x101. R1=0x1003

In the ARM instruction set what is the maximum branch distance for a Branch or Branch and Link instruction?

A. ±32MB

B. ±4MB

C. ±12KB

D. ±4KB

The automatic removal of a cache line from a cache to free the location is known as cache line:

A. Coherency

B. Pre-fetch

C. Eviction

D. Allocation

Which one of the following features must any processor support to conform to the ARMv7-A architecture?

A. NEON (Advanced SIMD)

B. Thumb-2 technology

C. TrustZone (Security Extensions)

D. Generic Interrupt Controller

LDREX and STREX were introduced in which ARM architecture version?

A. ARMv5TE

B. ARMv6

C. ARMv6K

D. ARMv7

The Performance Monitoring Unit (PMU) of a Cortex-A9 processor permits direct measurement of which one of the following?

A. Cache Size

B. Clock Speed

C. Program size

D. Numbers of instructions executed